The present disclosure relates to a technology for gating power supply in a semiconductor integrated circuit device.
Power gating is one of techniques for reducing power consumption of a semiconductor integrated circuit device. Through the power gating, internal circuitry of a semiconductor integrated circuit device is divided into a plurality of power domains (circuit blocks), and power supply to non-operating power domains is shut off, thereby reducing leakage current that leads to an increase of power consumption. The power gating uses a power switch that controls switching between electrical connection and disconnection between global power supply lines provided for the entire circuit arranged in a chip and local power supply lines provided for circuits of power domains.
Japanese Unexamined Patent Publication No. 2010-153535 discloses a configuration comprising multiple power switches, which are connected in a chain state. When power supply to a power domain to which power has been shut off is resumed, there occurs a problem of unstable operations of a semiconductor integrated circuit device due to lowered voltage of global power supply lines caused by an increase in current (rush current) flowing into the power domain. According to Japanese Unexamined Patent Publication No. 2010-153535, the rush current is reduced by sequentially turning on the power switches that are connected in the chain state.